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1 at49lv1025 plcc top view 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 i/o12 i/o11 i/o10 i/o9 i/o8 gnd nc i/o7 i/o6 i/o5 i/o4 a13 a12 a11 a10 a9 gnd nc a8 a7 a6 a5 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 i/o3 i/o2 i/o1 i/o0 oe nc a0 a1 a2 a3 a4 i/o13 i/o14 i/o15 ce nc nc vcc we nc a15 a14 features ? single-voltage operation ?3v read ? 3.1v programming fast read access time ? 55 ns internal program control and timer 8k word boot block with lockout fast erase cycle time ? 10 seconds word-by-word programming ? 20 s/word typical hardware data protection data polling for end of program detection small 10 x 14 mm vsop package typical 10,000 write cycles description the at49lv1024 and the at49lv1025 are 3-volt only in-system flash memories. their 1 megabit of memory is organized as 65,536 words by 16 bits. manufactured with atmel?s advanced nonvolatile cmos technology, the devices offer access times to 55 ns with power dissipation of just 90 mw over the commercial temperature range. the only difference between the at49lv1024 and the at49lv1025 is the package. to allow for simple in-system reprogrammability, the at49lv1024/1025 does not require high input voltages for programming. three-volt-only commands determine the read and programming operation of the device. reading data out of the device is simi- lar to reading from an eprom. reprogramming the at49lv1024/1025 is performed rev. 1278d?07/01 1-megabit (64k x 16) 3-volt only flash memory at49lv1024 at49lv1025 pin configurations pin name function a0 - a15 addresses ce chip enable oe output enable we write enable i/o0 - i/o15 data inputs/outputs nc no connect (continued) at49lv1024 vsop top view type 1 10 x 14 mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 a9 a10 a11 a12 a13 a14 a15 nc we vcc nc ce i/o15 i/o14 i/o13 i/o12 i/o11 i/o10 i/o9 i/o8 gnd a8 a7 a6 a5 a4 a3 a2 a1 a0 oe i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 gnd
2 at49lv1024/1025 1278d ? 07/01 by erasing a block of data (entire chip or main memory block) and then programming on a word by word basis. the typical word programming time is a fast 20 s. the end of a program cycle can be optionally detected by the data polling feature. once the end of a byte program cycle has been detected, a new access for a read or program can begin. the typical number of program and erase cycles is in excess of 10,000 cycles. the optional 8k word boot block section includes a reprogramming write lock out feature to provide data integrity. the boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being erased or reprogrammed. block diagram device operation read: the at49lv1024/1025 is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high-impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in preventing bus contention. chip erase: when the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase together from the same chip erase command (see command definitions table). if the boot block lockout function has been enabled, data in the boot section will not be erased. however, data in the main memory section will be erased. after a chip erase, the device will return to the read mode. main memory erase: as an alternative to the chip erase, a main memory block erase can be performed, which will erase all words not located in the boot block region to an ffffh. data located in the boot region will not be changed during a main memory block erase. the main memory erase command is a six-bus cycle operation. the address (5555h) is latched on the falling edge of the sixth cycle while the 30h data input is latched on the rising edge of we . the main memory erase starts after the rising edge of we of the sixth cycle. please see main memory erase cycle waveforms. the main memory erase operation is internally controlled; it will automatically time to completion. word programming: once the memory array is erased, the device is programmed (to a logic ? 0 ? ) on a word-by-word basis. please note that a data ? 0 ? cannot be pro- grammed back to a ? 1 ? ; only erase operations can convert ? 0 ? s to ? 1 ? s. programming is accomplished via the internal device command register and is a four-bus cycle opera- tion (please refer to the command definitions table). the device will automatically generate the required internal program pulses. oe, ce, and we logic y decoder x decoder input/output buffers data latch y-gating optional boot block (8k words) main memory (56k words) oe we ce address inputs vcc gnd data inputs/outputs i/o15 - i/o0 16 2000h 1fffh 0000h ffffh
3 at49lv1024/1025 1278d ? 07/01 the program cycle has addresses latched on the falling edge of we or ce , whichever occurs last, and the data latched on the rising edge of we or ce , whichever occurs first. programming is completed after the specified t bp cycle time. the data polling feature may also be used to indicate the end of a program cycle. boot block programming lockout: the device has one designated block that has a programming lockout feature. this feature prevents programming of data in the designated block once the feature has been enabled. the size of the block is 8k words. this block, referred to as the boot block, can contain secure code that is used to bring up the system. enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. this feature does not have to be activated; the boot block ? s usage as a write-protected region is optional to the user. the address range of the boot block is 0000h to 1fffh. once the feature is enabled, the data in the boot block can no longer be erased or pro- grammed. data in the main memory block can still be changed through the regular programming method and can be erased using either the chip erase or the main mem- ory block erase command. to activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. please refer to the command definitions table. boot block lockout detection: a software method is available to determine if programming of the boot block section is locked out. when the device is in the software product identification mode (see software product identification entry and exit sections) a read from address location 0002h will show if programming the boot block is locked out. if the data on i/o0 is low, the boot block can be programmed; if the data on i/o0 is high, the program lockout feature has been activated and the block cannot be pro- grammed. the software product identification exit code should be used to return to standard operation. product identification: the product identification mode identifies the device and manufacturer as atmel. it may be accessed by hardware or software operation. the hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the atmel product. for details, see ? operating modes ? (for hardware operation) or ? software product identi- fication entry/exit ? on page 11. the manufacturer and device code is the same for both modes. data polling: the at49lv1024/1025 features data polling to indicate the end of a program or erase cycle. during a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on i/o7. once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. data polling may begin at any time during the program cycle. toggle bit: in addition to data polling, the at49lv1024/1025 provides another method for determining the end of a program or erase cycle. during a program or erase operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examining the toggle bit may begin at any time during a pro- gram cycle. hardware data protection: hardware features protect against inadvertent writes to the at49lv1024/1025 in the following ways: (a) v cc sense: if v cc is below 1.8v (typical), the program function is inhibited. (b) program inhibit: holding any one of oe low, ce high or we high inhibits program cycles. (c) noise filter: pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle.
4 at49lv1024/1025 1278d ? 07/01 notes: 1. the data format in each bus cycle is as follows: i/o15 - i/o8 (don ? t care); i/o7 - i/o0 (hex). the address format in each bus cycle is as follows: a15 - a0 (hex); a15 (don ? t care). 2. the 8k word boot sector has the address range 00000h to 1fffh. 3. either one of the product id exit commands can be used. command definition (in hex) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr data addr data addr data addr data addr data addr data read 1 addr d out chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 main memory erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 30 word program 4 5555 aa 2aaa 55 5555 a0 addr d in boot block lockout (2) 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 40 product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (3) 3 5555 aa 2aaa 55 5555 f0 product id exit (3) 1xxxxf0 absolute maximum ratings* temperature under bias ................................ -55 c to +125 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe with respect to ground ...................................-0.6v to +13.5v
5 at49lv1024/1025 1278d ? 07/01 note: 1. minimum programming voltage is 3.1v. notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. 4. manufacturer code: 001fh; device code: 0087h. 5. see details under ? software product identification entry/exit ? on page 11. note: 1. in the erase mode, i cc is 40 ma. dc and ac operating range at49lv1024/1025-55 at49lv1024/1025-70 at49lv1024/1025-90 operating temperature (case) com. 0 c - 70 c0 c - 70 c0 c - 70 c ind. -40 c - 85 c v cc power supply 3.0v to 3.6v (1) 3.0v to 3.6v (1) 3.0v to 3.6v (1) operating modes mode ce oe we ai i/o read v il v il v ih ai d out program (2) v il v ih v il ai d in standby/write inhibit v ih x (1) xxhigh-z program inhibit x x v ih program inhibit x v il x output disable x v ih xhigh-z product identification hardware v il v il v ih a1 - a15 = v il , a9 = v h (3) , a0 = v il manufacturer code (4) a1 - a15 = v il , a9 = v h (3) , a0 = v ih device code (4) software (5) a0 = v il , a1 - a15 = v il manufacturer code (4) a0 = v ih , a1 - a15 = v il device code (4) dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 10.0 a i lo output leakage current v i/o = 0v to v cc 10.0 a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc com. 40.0 a ind. 130.0 a i sb2 v cc standby current ttl ce = 2.0v to v cc 0.5 ma i cc (1) v cc active current f = 5 mhz; i out = 0 ma 25.0 ma v il input low voltage 0.6 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh1 output high voltage i oh = -400 a 2.4 v
6 at49lv1024/1025 1278d ? 07/01 ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce , whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. ac read characteristics symbo l parameter at49lv1024/1025-55 at49lv1024/1025-70 at49lv1024/1025-90 units min max min max min max t acc address to output delay 55 70 90 ns t ce (1) ce to output delay 55 70 90 ns t oe (2) oe to output delay 30 35 0 40 ns t df (3)(4) ce or oe to output float 025025025ns t oh output hold from oe , ce or address, whichever occurred first 000ns
7 at49lv1024/1025 1278d ? 07/01 input test waveforms and measurement level t r , t f < 5 ns output test load note: 1. this parameter is characterized and is not 100% tested. 2.4v 0.4v output pin 3.0v 30 pf 1.8k 1.3k pin capacitance f = 1 mhz, t = 25 c (1) symbol typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v
8 at49lv1024/1025 1278d ? 07/01 ac word load waveforms we controlled ce controlled ac word load characteristics symbol parameter min max units t as , t oes address, oe setup time 0 ns t ah address hold time 70 ns t cs chip select setup time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )70ns t ds data setup time 70 ns t dh , t oeh data, oe hold time 0 ns t wph write pulse width high 50 ns t dh t ds t as t ah t wp ce address data in oe t oes t oeh we t cs t ch t wph t dh t ds t as t ah t wp we address data in oe t oes t oeh ce t cs t ch t wph
9 at49lv1024/1025 1278d ? 07/01 program cycle waveforms main memory or chip erase cycle waveforms notes: 1. oe must be high only when we and ce are both low. 2. for chip erase, the address should be 10h. for a main memory erase, the data should be 30h. program cycle characteristics symbol parameter min typ max units t bp word programming time 20 50 s t as address setup time 0 ns t ah address hold time 70 ns t ds data setup time 70 ns t dh data hold time 0 ns t wp write pulse width 70 ns t wph write pulse width high 50 ns t ec erase cycle time 1.5 5 seconds a0-a15 oe aa 80 note 2 55 55 5555 5555 5555 aa word 0 word 1 word 2 word 3 word 4 word 5 2aaa 2aaa t wph t wp ce we a0-a15 data t as t ah t ec t dh t ds 5555
10 at49lv1024/1025 1278d ? 07/01 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ? ac read characteristics ? on page 6. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ? ac read characteristics ? on page 6. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns
11 at49lv1024/1025 1278d ? 07/01 software product identification entry (1) software product identification exit (1) notes: 1. data format: i/o15 - i/o8 (don ? t care); i/o7 - i/o0 (hex); address format: a15 - a0 (hex); a15 (don ? t care). 2. a1 - a15 = v il . manufacturer code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code: 001fh device code: 0087h load data aa to address 5555 load data 55 to address 2aaa load data 90 to address 5555 enter product identification mode (2)(3)(5) load data aa to address 5555 load data 55 to address 2aaa load data f0 to address 5555 exit product identification mode (4) or load data f0 to any address exit product identification mode (4)
12 at49lv1024/1025 1278d ? 07/01 boot block lockout enable algorithm (1) notes: 1. data format: i/o15 - i/o8 (don ? t care); i/o7 - i/o0 (hex); address format: a15 - a0 (hex); a15 (don ? t care). 2. boot block lockout feature enabled. load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40 to address 5555 pause 1 second (2)
13 at49lv1024/1025 1278d ? 07/01 at49lv1024 ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 55 25 0.04 at49lv1024-55vc 40v commercial (0 to 70 c) 70 25 0.04 at49lv1024-70vc 40v commercial (0 to 70 c) 90 25 0.04 at49lv1024-90vc 40v commercial (0 to 70 c) 25 0.13 at49lv1024-90vi 40v industrial (-40 to 85 c) at49lv1025 ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 55 25 0.04 AT49LV1025-55JC 44j commercial (0 to 70 c) 70 25 0.04 at49lv1025-70jc 44j commercial (0 to 70 c) 90 25 0.04 at49lv1025-90jc 44j commercial (0 to 70 c) 25 0.13 at49lv1025-90ji 44j industrial (-40 to 85 c) package type 40v 40-lead, thin small outline package (vsop) (10 mm x 14 mm) 44j 44-lead, plastic, j-leaded chip carrier package (plcc)
packaging information 14 at49lv1024/1025 1278d ? 07/01 *controlling dimension: millimeters .045(1.14) x 45 pin no. 1 identify .045(1.14) x 30 - 45 .012(.305) .008(.203) .021(.533) .013(.330) .630(16.0) .590(15.0) .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .500(12.7) ref sq .032(.813) .026(.660) .050(1.27) typ .022(.559) x 45 max (3x) .656(16.7) .650(16.5) .695(17.7) .685(17.4) sq sq 40v , 40-lead, plastic thin small outline package (vsop) dimensions in millimeters and (inches)* 44j , 44-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) jedec standard ms-018 ac
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